In modern semiconductor device applications, numerous individual devices are packed onto a single small area of a semiconductor substrate. Many of these individuals devices need to be electrically isolated from one another. One method of accomplishing such isolation is to form a trenched isolation region between adjacent devices. Such trenched isolation region will generally comprise a trench or cavity formed within the substrate and filled with an insulative material, such as, for example, silicon dioxide. Trench isolation regions are commonly divided into three categories: shallow trenches (trenches less than about one micron deep); moderate depth trenches (trenches of about one to about three microns deep); and deep trenches (trenches greater than about three microns deep).
Prior art methods for forming trench structures are described with reference to FIGS. 1-12. Referring to FIG. 1, a semiconductor wafer fragment 10 is shown at a preliminary stage of a prior art processing sequence. Wafer fragment 10 comprises a semiconductive material 12 upon which is formed a layer of oxide 14, a layer of nitride 16, and a patterned layer of photoresist 18. Semiconductive material 12 commonly comprises monocrystalline silicon which is lightly doped with a conductivity-enhancing dopant. To aid in interpretation of the claims that follow, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Oxide layer 14 typically comprises silicon dioxide, and nitride layer 16 typically comprises silicon nitride. Nitride layer 16 is generally from about 400 Angstroms thick to about 920 Angstroms thick.
Referring to FIG. 2, patterned photoresist layer 18 is used as a mask for an etching process. The etch is typically conducted utilizing dry plasma conditions and CH.sub.2 F.sub.2 /CF.sub.4 chemistry. Such etching effectively etches both silicon nitride layer 16 and pad oxide layer 14 to form openings 20 extending therethrough. Openings 20 comprise peripheries defined by nitride sidewalls 17 and oxide sidewalls 15. The etching stops upon reaching silicon substrate 12.
Referring to FIG. 3, a second etch is conducted to extend openings 20 into silicon substrate 12. The second etch is commonly referred to as a "trench initiation etch." The trench initiation etch is typically a timed dry plasma etch utilizing CF.sub.4 HBr, and typically extends openings 20 to less than or equal to about 500 Angstroms into substrate 12. A purpose of the trench initiation etch can be to clean an exposed surface of silicon substrate 12 within openings 20 (i.e., to remove defects and polymer material) prior to final trenching into substrate 12. Another purpose of the trench initiation etch can be to form polymer over exposed sidewall edges 15 and 17 of oxide layer 1411 and nitride layer 16, respectively. Such polymer can alleviate erosion of sidewall edges 15 and 17 during subsequent etching of substrate 12.
Referring to FIG. 4, a third etch is conducted to extend openings 20 further into substrate 12 and thereby form trenches within substrate 12. Extended openings 20 comprise a periphery 22 defined by substrate 12. The third etch typically utilizes an etchant consisting entirely of HBr, and is typically a timed etch. The timing of the etch is adjusted to form trenches within substrate 12 to a desired depth. For instance, if openings 20 are to be shallow trenches, the third etch will be timed to extend openings 20 to a depth of less than or equal to about one micron.
Referring to FIG. 5, photoresist layer 18 (FIG. 4) is removed and a first oxide layer 24 is thermally grown within openings 20 and along the periphery 22 (FIG. 4) defined by silicon substrate 12. The growth of oxide layer 24 can form small bird's beak regions 26 underlying sidewall edges 17 of nitride layer 16.
Referring to FIG. 6, a high density plasma oxide 28 is formed to fill openings 20 (FIG. 5) and overlie nitride layer 16. High density plasma oxide 28 merges with oxide layer 24 (FIG. 5) to form oxide plugs 30 within openings 20 (FIG. 5). Oxide plugs 30 have laterally outermost peripheries 33 within openings 20.
Referring to FIG. 7, wafer fragment 10 is subjected to planarization (such as, for example, chemical-mechanical polishing) to planarize an upper surface of oxide plugs 30. The planarization stops at an upper surface of nitride layer 16.
Referring to FIG. 8, nitride layer 16 is removed to expose pad oxide layer 14 between oxide plugs 30.
Referring to FIG. 9, pad oxide layer (FIG. 8) is removed. The removal of the pad oxide layer leaves dips 32 at edges of oxide plugs 30.
Referring to FIG. 10, a sacrificial oxide layer 34 is grown over substrate 12 and between oxide plugs 30.
Referring to FIG. 11, sacrificial oxide layer 34 (FIG. 10) is removed. Formation and removal of sacrificial oxide layer 34 can be utilized to clean a surface of substrate 12 between oxide plugs 30. As such surface of substrate 12 can be ultimately utilized to form an active area of a transistor device, it is desired that the surface be substantially free of defects. The removal of sacrificial oxide layer 34 can also undesirably exacerbate dips 32.
Referring to FIG. 12, a silicon dioxide layer 36 is regrown between oxide plugs 30, and a polysilicon layer 38 is formed over oxide plugs 30 and oxide layer 36. Polysilicon layer 38 can ultimately be formed into a word line comprising transistor gate regions. Such transistor gate regions can lie between oxide plugs 30. Plugs 30 can then function as trenched isolation regions between transistor devices. Dips 32 can undesirably result in formation of parasitic devices adjacent the transistor devices and ultimately have an effect of lowering a threshold voltage for the transistor devices. Accordingly, it would be desirable to alleviate dips 32. Dips 32 can also interfere with subsequent fabrication processes and, for this reason as well, it would be desirable to alleviate dips 32.